Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Various methods of forming transistors on a semiconductor substrate are known in the art. Generally, transistors are isolated from each other by insulating or isolation structures.
One method of forming insulating structures and defining source and drain regions is by utilizing a shallow trench isolation (STI) process. A conventional STI process typically includes the following simplified steps. First, a silicon nitride layer is thermally grown or deposited onto the silicon substrate. Next, using a lithography and etch process, the silicon nitride layer is selectively removed to produce a pattern where transistor source/drain areas are to be located. After patterning the source/drain areas, the substrate is etched to form trenches. After the trenches are formed, a liner oxide is thermally grown on the exposed surfaces of the trench. The liner oxide is typically formed at a very high temperature in a hydrochloric acid (HCI) ambient. An insulative material such as silicon dioxide (SiO2) is blanket deposited over the nitride layer and the liner oxide within the trench. The insulative material is polished to create a planar surface. The nitride layer is subsequently removed to leave the oxide structures within the trenches.
Shallow trench isolation (STI) structures are utilized in strained silicon (SMOS) processes. SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response, and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer.
Theoretical calculations indicate that strained silicon layers in biaxial tension should exhibit higher electron and hole mobilities than do bulk silicon layers. It has been theoretically and experimentally demonstrated that mobilities are enhanced when the silicon layer is grown pseudomorphically on relaxed silicon germanium, which has a larger in-plane lattice constant than bulk silicon. Enhanced performance is demonstrated in SMOS transistors with channel regions formed by strained silicon on relaxed silicon germanium as discussed in “Strained Dependence of the Performance Enhancement in Strained-Si n-MOSFETS”, J. Welser, et al., IEDM'94, p. 373, 1994 and “Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETS”, K. Rim, et al., IEDM'95, p. 517, 1995.
The silicon germanium lattice associated with the silicon germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another.
Relaxed silicon has a conductive band that contains six equal valence bands. The application of tensile strain to the silicon causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, the lower energy bands offer less resistance to electron flow. In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
STI structures are the state-of-the-art isolation structures that have been widely applied to very large scale integrated (VLSI) and ultra large scale (ULSI) integrated circuits. One problem associated with STI structures involves the formation of sharp corners at the top of the trenches, which can result in transistor leakage currents and degraded gate oxide integrity. To avoid these problems, semiconductor fabrication techniques have been used to round the corners of such trenches to increase the radius of curvature and thereby decrease the electric field at the corners of the trenches.
Conventional processes have rounded the corners of the trenches by oxidizing the entire inner surface of the newly formed trench (e.g., by forming an oxide liner before filling the trench). Generally, the exposed corners of the silicon layer associated with the trenches oxidize faster than a flat surface in the silicon layer, thus forming a rounded upper corner at the top of the trench. This oxidation process is referred to as a liner oxidation process.
Using liner oxidation to achieve corner rounding in strained silicon devices can result in additional problems due to the presence of the silicon germanium layer under the active (strained) silicon layer. In silicon/silicon germanium devices, the shallow trench is etched through the silicon layer (approximately 200 Å) into the silicon germanium layer to achieve a total trench depth of between approximately 2,000–4,000 Å. When the exposed portion of the silicon germanium on the sidewalls of the newly formed trench is oxidized during the process of rounding the corners, the presence of germanium dramatically increases the oxidation rate relative to bulk silicon, thereby resulting in a non-uniform oxide thickness between the silicon layer and the silicon germanium layer.
Another problem related to liner oxidation in SMOS devices is germanium build-up. The build-up of germanium essentially forms a high concentration germanium layer along the side walls and bottom of the trenches between the liner oxide and the silicon germanium layer. The high concentration germanium layer can change the electrical characteristics of the STI structure. One change in electrical characteristics can be a higher junction leakage.
The use of germanium in SMOS processes can also cause germanium contamination problems for IC structures, layers, and equipment. In particular, germanium outgassing or outdiffusion can contaminate various components associated with the fabrication equipment and integrated circuit structures associating with the processed wafer. Further, germanium outgassing can negatively impact the formation of thin films.
Germanium outgassing can be particularly problematic at the very high temperatures and HCI ambient environments associated with the liner of a shallow trench isolation (STI) structure. For example, conventional STI liner oxide processes can utilize temperatures of approximately 1000° C., which act to enhance germanium outgassing.
Thus, there is a need for an STI structure with a liner that does not have a non-uniform thickness between the silicon and the silicon germanium layers. Further still, there is a need for a process of forming high quality oxides with good compatibility and that are not susceptible to germanium outgassing. Further still, there is a need for an efficient SMOS trench liner formation process. Yet further, there is a need for a liner formation process that is not as susceptible to a high concentration of germanium between the silicon dioxide liner and the silicon germanium layer. Further still, there is a need for an STI process that does not utilize high temperature to thermally grow liners.